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» Processor Architectures for Ontogenesis
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RTSS
2007
IEEE
15 years 6 months ago
Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers a...
Jakob Rosen, Alexandru Andrei, Petru Eles, Zebo Pe...
75
Voted
RTSS
2007
IEEE
15 years 6 months ago
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts
In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. To separate real-time and non-real-time hardware interrupts by hardware, we...
Miao Liu, Zili Shao, Meng Wang, Hongxing Wei, Tian...
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
15 years 6 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...
SBACPAD
2007
IEEE
128views Hardware» more  SBACPAD 2007»
15 years 6 months ago
Node Level Primitives for Parallel Exact Inference
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
Yinglong Xia, Viktor K. Prasanna
FPL
2007
Springer
105views Hardware» more  FPL 2007»
15 years 6 months ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl