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» Processor Architectures for Ontogenesis
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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 10 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
IPPS
2005
IEEE
15 years 10 months ago
Enhancing NIC Performance for MPI using Processing-in-Memory
Processing-in-Memory (PIM) technology encompasses a range of research leveraging a tight coupling of memory and processing. The most unique features of the technology are extremel...
Arun Rodrigues, Richard C. Murphy, Ron Brightwell,...
ISPASS
2005
IEEE
15 years 10 months ago
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection
Simulation-based microarchitecture research is often hindered by the slow speed of simulators. In this work, we propose a novel statistical technique to identify highly representa...
Ram Srinivasan, Jeanine Cook, Shaun Cooper
VISUALIZATION
2005
IEEE
15 years 10 months ago
General Purpose Computation on Graphics Hardware
The rapid increase in the performance of graphics hardware, coupled with recent improvements in its programmability, have made graphics hardware a compelling platform for computat...
Aaron E. Lefohn, Ian Buck, Patrick S. McCormick, J...
SC
2005
ACM
15 years 10 months ago
A Scalable Distributed Parallel Breadth-First Search Algorithm on BlueGene/L
Many emerging large-scale data science applications require searching large graphs distributed across multiple memories and processors. This paper presents a distributed breadthï¬...
Andy Yoo, Edmond Chow, Keith W. Henderson, Will Mc...