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» Processor Architectures for Ontogenesis
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CGO
2003
IEEE
15 years 5 months ago
Dynamic Trace Selection Using Performance Monitoring Hardware Sampling
Optimizing programs at run-time provides opportunities to apply aggressive optimizations to programs based on information that was not available at compile time. At run time, prog...
Howard Chen, Wei-Chung Hsu, Dong-yuan Chen
DFT
2003
IEEE
132views VLSI» more  DFT 2003»
15 years 5 months ago
Level-Hybrid Optoelectronic TESH Interconnection Network
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
Vijay K. Jain, Glenn H. Chapman
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 5 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
15 years 5 months ago
Phase Tracking and Prediction
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...
Timothy Sherwood, Suleyman Sair, Brad Calder
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
15 years 5 months ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...