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» Processor Architectures for Ontogenesis
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ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
15 years 4 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 4 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy
INFOCOM
1996
IEEE
15 years 4 months ago
Congestion-Oriented Shortest Multipath Routing
We present a framework for the modeling of multipath routing in connectionless networks that dynamically adapt to network congestion. The basic routing protocol uses a short-term ...
Shree Murthy, J. J. Garcia-Luna-Aceves
ASPLOS
1996
ACM
15 years 4 months ago
The Structure and Performance of Interpreters
Interpreted languages have become increasingly popular due to demands for rapid program development, ease of use, portability, and safety. Beyond the general impression that they ...
Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker...
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 4 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain