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» Processor Architectures for Ontogenesis
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ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 3 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
DATE
2010
IEEE
147views Hardware» more  DATE 2010»
15 years 2 months ago
Detecting/preventing information leakage on the memory bus due to malicious hardware
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...
Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok ...
USS
2008
15 years 2 months ago
Towards Application Security on Untrusted Operating Systems
Complexity in commodity operating systems makes compromises inevitable. Consequently, a great deal of work has examined how to protect security-critical portions of applications f...
Dan R. K. Ports, Tal Garfinkel
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
15 years 1 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
ASPLOS
2008
ACM
15 years 1 months ago
How low can you go?: recommendations for hardware-supported minimal TCB code execution
We explore the extent to which newly available CPU-based security technology can reduce the Trusted Computing Base (TCB) for security-sensitive applications. We find that although...
Jonathan M. McCune, Bryan Parno, Adrian Perrig, Mi...