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» Processor Architectures for Ontogenesis
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ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
15 years 6 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 6 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
15 years 6 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
ICS
2007
Tsinghua U.
15 years 6 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
ICS
2007
Tsinghua U.
15 years 6 months ago
Automatic nonblocking communication for partitioned global address space programs
Overlapping communication with computation is an important optimization on current cluster architectures; its importance is likely to increase as the doubling of processing power ...
Wei-Yu Chen, Dan Bonachea, Costin Iancu, Katherine...