2700 search results - page 8 / 540 » Processor Architectures for Ontogenesis |
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
MICRO
2000
IEEE
14 years 9 months ago
2000
IEEE
The popularity of the Internet and the emergence of broadband access networks is fueling the development of communications processors -- devices that integrate processing, network...
CORR
2010
Springer
14 years 9 months ago
2010
Springer
We propose different implementations of the sparse matrix
119
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DSD
2011
IEEE
13 years 9 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
151
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SIGOPS
2011
14 years 4 months ago
2011
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...