2700 search results - page 92 / 540 » Processor Architectures for Ontogenesis |
132
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ASAP
2006
IEEE
15 years 8 months ago
2006
IEEE
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
145
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DAC
2006
ACM
15 years 8 months ago
2006
ACM
Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even `trusted so...
109
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LCN
2003
IEEE
15 years 9 months ago
2003
IEEE
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...
145
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HPCA
2000
IEEE
15 years 9 months ago
2000
IEEE
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
141
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...