142 search results - page 10 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
MST
2002
14 years 9 months ago
2002
Abstract. Blockwise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is f...
117
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IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
100
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WMPI
2004
ACM
15 years 2 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
100
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CALCO
2007
Springer
15 years 3 months ago
2007
Springer
Much current work on modelling and verifying microprocessors can accommodate pipelined and superscalar processors. However, superscalar and pipelined processors are no longer state...