Sciweavers

142 search results - page 12 / 29
» Processor Memory Co-Exploration on Multiple Abstraction Leve...
Sort
View
IPPS
2006
IEEE
15 years 5 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
SC
2009
ACM
15 years 5 months ago
Increasing memory miss tolerance for SIMD cores
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called “di...
David Tarjan, Jiayuan Meng, Kevin Skadron
LCPC
2005
Springer
15 years 4 months ago
Optimizing Packet Accesses for a Domain Specific Language on Network Processors
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Ro...
USENIX
1994
15 years 8 days ago
TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems
TreadMarks is a distributed shared memory DSM system for standard Unix systems such as SunOS and Ultrix. This paper presents a performance evaluation of TreadMarks running on Ultr...
Peter J. Keleher, Alan L. Cox, Sandhya Dwarkadas, ...
MTA
2006
115views more  MTA 2006»
14 years 11 months ago
Cache modeling and optimization for portable devices running MPEG-4 video decoder
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...
Abu Asaduzzaman, Imad Mahgoub