142 search results - page 16 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
72
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IISWC
2009
IEEE
15 years 4 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
116
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TVLSI
2010
14 years 4 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
103
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IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
SIGMETRICS
2011
ACM
14 years 9 days ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
HIPEAC
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...