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PC
1998
153views Management» more  PC 1998»
14 years 9 months ago
Compilation Techniques for Out-of-Core Parallel Computations
The difficulty of handling out-of-core data limits the performance of supercomputers as well as the potential of the parallel machines. Since writing an efficient out-of-core ve...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
15 years 3 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
PROCEDIA
2010
148views more  PROCEDIA 2010»
14 years 4 months ago
SysCellC: a data-flow programming model on multi-GPU
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
Dominique Houzet, Sylvain Huet, Anis Rahman
PLDI
2009
ACM
15 years 4 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
112
Voted
CADE
1998
Springer
15 years 1 months ago
System Description: card TAP: The First Theorem Prover on a Smart Card
Abstract. We present the first implementation of a theorem prover running on a smart card. The prover is written in Java and implements a dual tableau calculus. Due to the limited ...
Rajeev Goré, Joachim Posegga, Andrew Slater...