142 search results - page 2 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
CASES
2008
ACM
14 years 11 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
112
click to vote
IESS
2009
Springer
14 years 7 months ago
2009
Springer
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
103
click to vote
ISCAS
2011
IEEE
14 years 1 months ago
2011
IEEE
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...