142 search results - page 3 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
TC
1998
14 years 9 months ago
1998
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
VLSISP
2008
14 years 9 months ago
2008
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
ISCA
2007
IEEE
14 years 9 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
IWCC
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper, we present techniques and algorithms to improve the performance of various communication patterns on message-passing platforms where, for reasons of safety, user-le...
HPCA
2003
IEEE
15 years 9 months ago
2003
IEEE
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...