142 search results - page 7 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
PARLE
1994
15 years 1 months ago
1994
Abstract. As the disparity between processor and memory speed continues to widen, the exploitation of locality of reference in shared-memory multiprocessors becomes an increasingly...
VMCAI
2010
Springer
15 years 6 months ago
2010
Springer
Abstract. Device drivers often keep data in multiple data structures simultaneously while embedding list or tree related records into the records containing the actual data; this r...
70
Voted
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
Parallel programming on distributed memory systems is one of the most challenging research areas in parallel computingtoday. Objectbased parallel programming languages are an impor...
LCTRTS
1998
Springer
15 years 1 months ago
1998
Springer
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
CSREAESA
2003
14 years 11 months ago
2003
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...