142 search results - page 9 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
EH
2004
IEEE
15 years 1 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
81
Voted
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract: Existing multicore systems already provide deep levels of thread parallelism. Hybrid programming models and composability of parallel libraries are very active areas of r...
ISNN
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
ICPADS
2006
IEEE
15 years 3 months ago
2006
IEEE
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
IEEEPACT
2003
IEEE
15 years 2 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...