378 search results - page 13 / 76 » Processor Modeling for Hardware Software Codesign |
132
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CODES
2009
IEEE
15 years 7 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
DAC
2000
ACM
16 years 1 months ago
2000
ACM
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
106
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VEE
2012
ACM
13 years 8 months ago
2012
ACM
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
93
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ISCAS
2003
IEEE
15 years 5 months ago
2003
IEEE
Communication synthesis is an essential step in hardware/software co-synthesis: many embedded systems use automatic generation of interface for point to point communication or use...
117
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CODES
2005
IEEE
15 years 6 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...