Sciweavers

378 search results - page 20 / 76
» Processor Modeling for Hardware Software Codesign
Sort
View
111
Voted
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
15 years 4 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel
103
Voted
CODES
2008
IEEE
15 years 7 months ago
Cache-aware optimization of BAN applications
Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring ...
Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mi...
CODES
2005
IEEE
15 years 6 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
88
Voted
COMPSAC
2008
IEEE
15 years 7 months ago
Embedded Architecture Description Language
In the state-of-the-art hardware/software (HW/SW) codesign of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. S...
Juncao Li, Nicholas T. Pilkington, Fei Xie, Qiang ...
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
15 years 3 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...