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» Processor Modeling for Hardware Software Codesign
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ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
15 years 9 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
89
Voted
LCPC
1999
Springer
15 years 4 months ago
Compiling for Speculative Architectures
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
Seon Wook Kim, Rudolf Eigenmann
CODES
2005
IEEE
15 years 6 months ago
Microcoded coprocessor for embedded secure biometric authentication systems
We design and implement a cryptographic biometric authentication system using a microcoded architecture. The secure properties of the biometric matching process are obtained by me...
Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhe...
95
Voted
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 24 days ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
122
Voted
CODES
2007
IEEE
15 years 6 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas