378 search results - page 39 / 76 » Processor Modeling for Hardware Software Codesign |
69
Voted
FPL
2003
Springer
15 years 5 months ago
2003
Springer
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
113
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CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
The design and analysis of today’s complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applyin...
104
Voted
DAC
2003
ACM
16 years 1 months ago
2003
ACM
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...
112
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CODES
2006
IEEE
15 years 6 months ago
2006
IEEE
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
101
Voted
CGO
2004
IEEE
15 years 4 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...