378 search results - page 55 / 76 » Processor Modeling for Hardware Software Codesign |
105
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ICCAD
2001
IEEE
15 years 10 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
121
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ASPDAC
2010
ACM
14 years 11 months ago
2010
ACM
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
101
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IEEEPACT
2007
IEEE
15 years 8 months ago
2007
IEEE
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of paralle...
103
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MICRO
2008
IEEE
15 years 8 months ago
2008
IEEE
The advent of multicores presents a promising opportunity for speeding up sequential programs via profile-based speculative parallelization of these programs. In this paper we pr...
133
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DATE
2005
IEEE
15 years 7 months ago
2005
IEEE
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...