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» Processor Models for Retargetable Tools
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IWOMP
2007
Springer
15 years 5 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
SIGADA
2005
Springer
15 years 5 months ago
Temporal skeletons for verifying time
This paper presents an intermediate notation used in a framework for verification of real-time properties. The framework aims at overcoming the need for the framework user to hav...
Gustaf Naeser, Kristina Lundqvist, Lars Asplund
LCTRTS
2004
Springer
15 years 5 months ago
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
15 years 6 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
15 years 6 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...