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» Processor Models for Retargetable Tools
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91
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DAC
2005
ACM
16 years 18 days ago
Fine-grained application source code profiling for ASIP design
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...
93
Voted
DAC
2000
ACM
16 years 18 days ago
Synthesis and optimization of coordination controllers for distributed embedded systems
A main advantage of control composition with modal processes [4] is the enhanced retargetability of the composed behavior over a wide variety of target architectures. Unlike previ...
Pai H. Chou, Gaetano Borriello
DAC
2005
ACM
15 years 1 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
97
Voted
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 3 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 5 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...