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» Processor-time-optimal systolic arrays
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IPPS
2009
IEEE
15 years 4 months ago
Accelerating HMMer on FPGAs using systolic array based architecture
HMMer is a widely-used bioinformatics software package that uses profile HMMs (Hidden Markov Models) to model the primary structure consensus of a family of protein or nucleic aci...
Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan ...
ICRA
1994
IEEE
118views Robotics» more  ICRA 1994»
15 years 1 months ago
Developing Parallel Architectures for Range and Image Sensors
We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic ...
Shaori Guo, Wayne Luk, Penelope Probert
FPL
2009
Springer
98views Hardware» more  FPL 2009»
15 years 2 months ago
Optimal runtime reconfiguration strategies for systolic arrays
Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chambe...
JPDC
2000
58views more  JPDC 2000»
14 years 9 months ago
Mapping of Neural Network Models onto Systolic Arrays
Sudipta Mahapatra, Rabi N. Mahapatra