650 search results - page 110 / 130 » Profile-Driven Cache Management |
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
ISCA
2010
IEEE
14 years 11 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
116
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SIGMETRICS
2008
ACM
14 years 9 months ago
2008
ACM
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
163
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ICDE
2008
IEEE
15 years 11 months ago
2008
IEEE
- The embedding of positioning capabilities in mobile devices and the emergence of location-based applications have created novel opportunities for utilizing several types of multi...