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107
Voted
ICCD
2008
IEEE
124views Hardware» more  ICCD 2008»
16 years 10 days ago
Global bus route optimization with application to microarchitectural design exploration
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
Dae Hyun Kim, Sung Kyu Lim
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 9 days ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes
127
Voted
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
16 years 9 days ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
16 years 9 days ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
122
Voted
CHI
2010
ACM
15 years 10 months ago
Postcolonial computing: a lens on design and development
As our technologies travel to new cultural contexts and our designs and methods engage new constituencies, both our design and analytical practices face significant challenges. We...
Lilly Irani, Janet Vertesi, Paul Dourish, Kavita P...
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