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IEEEPACT
2006
IEEE
15 years 3 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
DAC
2003
ACM
15 years 10 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
CODES
2009
IEEE
15 years 4 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
DATE
2008
IEEE
165views Hardware» more  DATE 2008»
15 years 4 months ago
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
Ken W. Batcher, Robert A. Walker
ACL2
2006
ACM
15 years 3 months ago
Phylogenetic trees in ACL2
Biologists studying the evolutionary relationships between organisms use software packages to solve the computational problems they encounter. Several of these problems involve th...
Warren A. Hunt Jr., Serita M. Nelesen