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» Programmable Packet Scheduling
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FPL
2003
Springer
136views Hardware» more  FPL 2003»
15 years 4 months ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller
CF
2006
ACM
15 years 5 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
TVLSI
2008
157views more  TVLSI 2008»
14 years 11 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
88
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ICDCS
2003
IEEE
15 years 5 months ago
Compiler Scheduling of Mobile Agents for Minimizing Overheads
Mobile code carried by a mobile agent can automatically travel to several data sources in order to complete a designated program. Traditionally, most mobile agent systems [7][8][1...
Xiaotong Zhuang, Santosh Pande
NETWORK
2006
218views more  NETWORK 2006»
14 years 11 months ago
Quality of service for packet telephony over mobile ad hoc networks
IP telephony over mobile ad hoc networks is a topic of emerging interest in the research arena as one of the paths toward the fixed-mobile convergence in telecommunications networ...
Paolo Giacomazzi, Luigi Musumeci, Giuseppe Caizzon...