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FPL
2009
Springer
135views Hardware» more  FPL 2009»
15 years 7 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
212
Voted
JHSN
2002
68views more  JHSN 2002»
15 years 2 months ago
A theory of multi-channel schedulers for quality of service
A computer network consists of a set of computing nodes interconnected via communication channels. It is commonly assumed that, for each pair of network nodes u and v, there is at...
Jorge Arturo Cobb, Miaohua Lin
GLOBECOM
2007
IEEE
15 years 9 months ago
Enhancing QoS Support in IEEE 802.11e HCCA
—IEEE 802.11e standard develops a reference design to support the contention-free access. In the reference design, the packet transmission opportunity (TXOP) duration is calculat...
Qinglin Zhao, Danny H. K. Tsang
128
Voted
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 6 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
GLOBECOM
2007
IEEE
15 years 9 months ago
Optimal Batch Scheduling in DVB-S2 Satellite Networks
—In this paper we present a new theoretical model to assess the performance of a class of batch scheduling orders in a forward DVB-S2 satellite link. The scheduling order in a DV...
G. T. Peeters, Benny Van Houdt, Chris Blondia