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IFE
2010
87views more  IFE 2010»
14 years 7 months ago
A middleware for efficient stream processing in CUDA
This paper presents a middleware capable of out-of-order execution of kernels and data transfers for efficient stream processing in the compute unified device architecture (CUDA). ...
Shinta Nakagawa, Fumihiko Ino, Kenichi Hagihara
ICFP
2012
ACM
13 years 22 hour ago
Nested data-parallelism on the gpu
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
Lars Bergstrom, John H. Reppy
CORR
2011
Springer
211views Education» more  CORR 2011»
14 years 1 months ago
Programming Massively Parallel Architectures using MARTE: a Case Study
—Nowadays, several industrial applications are being ported to parallel architectures. These applications take advantage of the potential parallelism provided by multiple core pr...
Antonio Wendell De Oliveira Rodrigues, Fréd...
TGIS
2002
118views more  TGIS 2002»
14 years 9 months ago
A Dynamic Architecture for Distributing Geographic Information Services
Traditional GISystems are no longer appropriate for modern distributed, heterogeneous network environments due to their closed architecture, and their lack of interoperability, reu...
Ming-Hsiang Tsou, Barbara P. Buttenfield
ANCS
2007
ACM
15 years 1 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos