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159
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ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
15 years 12 days ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
CCGRID
2008
IEEE
15 years 9 months ago
Scheduling Asymmetric Parallelism on a PlayStation3 Cluster
Understanding the potential and implications of asymmetric multi-core processors for cluster computing is necessary, as these processors are rapidly becoming mainstream components...
Filip Blagojevic, Matthew Curtis-Maury, Jae-Seung ...
111
Voted
IEEEPACT
2008
IEEE
15 years 8 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
117
Voted
APPT
2007
Springer
15 years 8 months ago
Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors
It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on...
Zhiyong Yu, Zhiyi Yang, Fan Zhang, Zhiwen Yu, Tuan...
160
Voted
ISPAN
2002
IEEE
15 years 7 months ago
Automatic Processor Lower Bound Formulas for Array Computations
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequenc...
Peter R. Cappello, Ömer Egecioglu