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ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
15 years 3 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
IEEEPACT
2005
IEEE
15 years 3 months ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
WMPI
2004
ACM
15 years 3 months ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...
LCPC
2004
Springer
15 years 3 months ago
A Geometric Approach for Partitioning N-Dimensional Non-rectangular Iteration Spaces
Abstract. Parallel loops account for the greatest percentage of program parallelism. The degree to which parallelism can be exploited and the amount of overhead involved during par...
Arun Kejariwal, Paolo D'Alberto, Alexandru Nicolau...
ISHPC
2003
Springer
15 years 2 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos