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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 3 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ASPLOS
2008
ACM
14 years 11 months ago
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
Michal Wegiel, Chandra Krintz
ASPLOS
2008
ACM
14 years 11 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
VRCAI
2004
ACM
15 years 3 months ago
Explorative construction of virtual worlds: an interactive kernel approach
Despite steady research advances in many aspects of virtual reality, building and testing virtual worlds remains to be a very difficult process. Most virtual environments are stil...
Jinseok Seo, Gerard Jounghyun Kim
REFLECTION
2001
Springer
15 years 2 months ago
Performance and Integrity in the OpenORB Reflective Middleware
, are to address what we perceive as the most pressing shortcomings of current reflective middleware platforms. First, performance: in the worst case, this needs to be on a par wit...
Gordon S. Blair, Geoff Coulson, Michael Clarke, Ni...