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» Programming Configurable Multiprocessors
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PPL
2008
185views more  PPL 2008»
15 years 1 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
IPPS
2010
IEEE
14 years 11 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
105
Voted
MICRO
2010
IEEE
128views Hardware» more  MICRO 2010»
14 years 11 months ago
Adaptive and Speculative Slack Simulations of CMPs on CMPs
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...
Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, ...
160
Voted
CAL
2010
14 years 10 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
226
Voted
POPL
2009
ACM
16 years 2 months ago
The semantics of progress in lock-based transactional memory
Transactional memory (TM) is a promising paradigm for concurrent programming. Whereas the number of TM implementations is growing, however, little research has been conducted to p...
Rachid Guerraoui, Michal Kapalka