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ISVLSI
2003
IEEE
101views VLSI» more  ISVLSI 2003»
15 years 2 months ago
Energy Benefits of a Configurable Line Size Cache for Embedded Systems
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
PPOPP
2010
ACM
15 years 6 months ago
Lazy binary-splitting: a run-time adaptive work-stealing scheduler
We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing...
Alexandros Tzannes, George C. Caragea, Rajeev Baru...
TPDS
1998
157views more  TPDS 1998»
14 years 9 months ago
A Compiler Optimization Algorithm for Shared-Memory Multiprocessors
This paper presents a new compiler optimization algorithm that parallelizes applications for symmetric, sharedmemory multiprocessors. The algorithm considers data locality, parall...
Kathryn S. McKinley
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS
- It is attractive to use the OpenMP as a parallel programming model on a Multiprocessor System-On-Chip (MPSoC) because it is easy to write a parallel program in the OpenMP and the...
Woo-Chul Jeun, Soonhoi Ha
RV
2010
Springer
128views Hardware» more  RV 2010»
14 years 7 months ago
Reducing Configurations to Monitor in a Software Product Line
A product line is a family of programs where each program is defined by a unique combination of features. Product lines, like conventional programs, can be checked for safety prope...
Chang Hwan Peter Kim, Eric Bodden, Don S. Batory, ...