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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
15 years 6 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
FPL
2006
Springer
115views Hardware» more  FPL 2006»
15 years 1 months ago
Executing Hardware as Parallel Software for Picoblaze Networks
Multi-processor architectures have gained interest recently because of their ability to exploit programmable silicon parallelism at acceptable power-efficiency figures. Despite th...
Pengyuan Yu, Patrick Schaumont
HPCA
1998
IEEE
15 years 1 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
76
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IJCNN
2000
IEEE
15 years 2 months ago
Comparison of a Heuristic Dynamic Programming and a Dual Heuristic Programming Based Adaptive Critics Neurocontroller for a Turb
: This paper presents the design of a neurocontroller for a turbogenerator that augments/replaces the conventional Automatic Voltage Regulator (AVR) and the turbine governor. The n...
Ganesh K. Venayagamoorthy, Ronald G. Harley, Donal...
BIRTHDAY
2010
Springer
14 years 10 months ago
Model Checking Programmable Router Configurations
Programmable networks offer the ability to customize router behaviour at run time, thus providing new levels of flexibility for network administrators. We have developed a program...
Luca Zanolin, Cecilia Mascolo, Wolfgang Emmerich