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ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 2 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ISCA
1993
IEEE
92views Hardware» more  ISCA 1993»
15 years 1 months ago
The Detection and Elimination of Useless Misses in Multiprocessors
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, ...
JMLR
2006
105views more  JMLR 2006»
14 years 9 months ago
Parallel Software for Training Large Scale Support Vector Machines on Multiprocessor Systems
Parallel software for solving the quadratic program arising in training support vector machines for classification problems is introduced. The software implements an iterative dec...
Luca Zanni, Thomas Serafini, Gaetano Zanghirati
FCCM
1999
IEEE
134views VLSI» more  FCCM 1999»
15 years 2 months ago
Runlength Compression Techniques for FPGA Configurations
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
Scott Hauck, William D. Wilson
ASPLOS
2000
ACM
15 years 2 months ago
Slipstream Processors: Improving both Performance and Fault Tolerance
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...
Karthik Sundaramoorthy, Zachary Purser, Eric Roten...