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IISWC
2008
IEEE
15 years 4 months ago
PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors
The PARSEC benchmark suite was recently released and has been adopted by a significant number of users within a short amount of time. This new collection of workloads is not yet ...
Christian Bienia, Sanjeev Kumar, Kai Li
ISCA
2008
IEEE
89views Hardware» more  ISCA 2008»
15 years 4 months ago
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...
Radu Teodorescu, Josep Torrellas
HIPC
2005
Springer
15 years 3 months ago
Design and Implementation of the HPCS Graph Analysis Benchmark on Symmetric Multiprocessors
Graph theoretic problems are representative of fundamental computations in traditional and emerging scientific disciplines like scientific computing, computational biology and b...
David A. Bader, Kamesh Madduri
ICS
1993
Tsinghua U.
15 years 1 months ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
15 years 1 months ago
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
1 Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. How...
Mikael Väyrynen, Virendra Singh, Erik Larsson