974 search results - page 63 / 195 » Programming Configurable Multiprocessors |
115
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
ERSA
2007
14 years 11 months ago
2007
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
JISE
2002
14 years 9 months ago
2002
Load balancing and data locality are the two most important factors in the performance of parallel programs on distributed-memory multiprocessors. A good balancing scheme should e...
140
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CAL
2010
14 years 7 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
CORR
2011
Springer
14 years 4 months ago
2011
Springer
The memory consistency model is a fundamental system property characterizing a multiprocessor. The relative merits of strict versus relaxed memory models have been widely debated ...