974 search results - page 99 / 195 » Programming Configurable Multiprocessors |
140
Voted
CODES
2006
IEEE
15 years 8 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
126
Voted
ICS
2009
Tsinghua U.
15 years 7 months ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
121
click to vote
TC
2008
15 years 2 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
99
Voted
WDAG
2005
Springer
15 years 7 months ago
2005
Springer
Transactional Memory is a concurrent programming API in which concurrent threads synchronize via transactions (instead of locks). Although this model has mostly been studied in the...
102
Voted
SRDS
2003
IEEE
15 years 7 months ago
2003
IEEE
Replication is one of the prominent approaches for obtaining fault tolerance. Implementing replication on commodity hardware and in a transparent fashion, i.e., without changing t...