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ARCS
2009
Springer
15 years 4 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
ERSHOV
2009
Springer
15 years 4 months ago
Multi-level Virtual Machine Debugging Using the Java Platform Debugger Architecture
Abstract. Debugging virtual machines (VMs) presents unique challenges, especially meta-circular VMs, which are written in the same language they implement. Making sense of runtime ...
Thomas Würthinger, Michael L. Van De Vanter, ...
CGO
2008
IEEE
15 years 4 months ago
Latency-tolerant software pipelining in a production compiler
In this paper we investigate the benefit of scheduling non-critical loads for a higher latency during software pipelining. "Noncritical" denotes those loads that have s...
Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampso...
CGO
2008
IEEE
15 years 4 months ago
Automatic array inlining in java virtual machines
Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative ...
Christian Wimmer, Hanspeter Mössenböck
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
15 years 4 months ago
Implementing the Best Processor Cores
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...
Vamsi Boppana, Rahoul Varma, S. Balajee