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122
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DAC
2005
ACM
15 years 4 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
129
Voted
DAC
2007
ACM
16 years 3 months ago
Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...
Yongsoo Joo, Youngjin Cho, Donghwa Shin, Naehyuck ...
139
Voted
ISORC
2009
IEEE
15 years 9 months ago
Fault-Tolerance for Component-Based Systems - An Automated Middleware Specialization Approach
General-purpose middleware, by definition, cannot readily support domain-specific semantics without significant manual efforts in specializing the middleware. This paper prese...
Sumant Tambe, Akshay Dabholkar, Aniruddha S. Gokha...
IPPS
2009
IEEE
15 years 9 months ago
Annotation-based empirical performance tuning using Orio
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
Albert Hartono, Boyana Norris, Ponnuswamy Sadayapp...
116
Voted
DAC
2005
ACM
15 years 4 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...