627 search results - page 79 / 126 » Programming multi-core architectures using Data-Flow techniq... |
117
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
141
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ETS
2010
IEEE
15 years 3 months ago
2010
IEEE
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
132
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APPT
2009
Springer
15 years 9 months ago
2009
Springer
SIMD extension is one of the most common and effective technique to exploit data-level parallelism in today’s processor designs. However, the performance of SIMD architectures i...
115
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ASAP
1997
IEEE
15 years 6 months ago
1997
IEEE
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...
139
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DAGSTUHL
1996
15 years 3 months ago
1996
As partial evaluation gets more mature, it is now possible to use this program transformation technique to tackle realistic languages and real-size application programs. However, t...