627 search results - page 91 / 126 » Programming multi-core architectures using Data-Flow techniq... |
115
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EMSOFT
2007
Springer
15 years 8 months ago
2007
Springer
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
137
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DAC
2006
ACM
15 years 4 months ago
2006
ACM
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
104
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
117
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ATAL
2004
Springer
15 years 7 months ago
2004
Springer
The paper describes the architecture of Brown University’s agent, Botticelli, a finalist in the 2003 Trading Agent Competition in Supply Chain Management (TAC SCM). In TAC SCM,...
173
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FAABS
2004
Springer
15 years 7 months ago
2004
Springer
Abstract. The design of reactive systems must comply with logical correctness (the system does what it is supposed to do) and timeliness (the system has to satisfy a set of tempora...