627 search results - page 93 / 126 » Programming multi-core architectures using Data-Flow techniq... |
101
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DAGSTUHL
2006
15 years 3 months ago
2006
Abstract. In the context of an approach for reengineering legacy software systems at the architectural level, we present in this paper a reverse engineering methodology that uses a...
140
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ASPLOS
2004
ACM
15 years 7 months ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
133
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IPPS
2006
IEEE
15 years 8 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
122
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DAC
2010
ACM
15 years 6 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
116
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DAC
1995
ACM
15 years 6 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...