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IEEEPACT
2002
IEEE
15 years 4 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
IPPS
2002
IEEE
15 years 4 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
IPPS
2002
IEEE
15 years 4 months ago
Improving Performance of Multiple Sequence Alignment Analysis in Multi-Client Environments
This paper is concerned with the efficient execution of multiplesequence alignmentmethodsin a multipleclientenvironment. Multiple sequence alignment (MSA) is a computationally ex...
Ümit V. Çatalyürek, Eric Stahlber...
ICSE
2010
IEEE-ACM
15 years 4 months ago
A degree-of-knowledge model to capture source code familiarity
The size and high rate of change of source code comprising a software system make it difficult for software developers to keep up with who on the team knows about particular parts...
Thomas Fritz, Jingwen Ou, Gail C. Murphy, Emerson ...
FPL
2009
Springer
161views Hardware» more  FPL 2009»
15 years 3 months ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow