Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
Recent research results have seen the application of parallelizing techniques to high-level synthesis. In particular, the effect of speculative code transformations on mixed contr...
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santa...
Bigraphs are emerging as a (meta-)model for concurrent calculi, like CCS, ambients, πcalculus, and Petri nets. They are built orthogonally on two structures: a hierarchical place...
Giovanni Conforti, Damiano Macedonio, Vladimiro Sa...
We propose a new configuration language, component and service library, and compiler that make it easier to develop efficient sensor network applications. Our goal is the constr...
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...