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IPPS
2006
IEEE
15 years 3 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Using speculative computation and parallelizing techniques to improve scheduling of control based designs
Recent research results have seen the application of parallelizing techniques to high-level synthesis. In particular, the effect of speculative code transformations on mixed contr...
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santa...
ICALP
2005
Springer
15 years 3 months ago
Spatial Logics for Bigraphs
Bigraphs are emerging as a (meta-)model for concurrent calculi, like CCS, ambients, πcalculus, and Petri nets. They are built orthogonally on two structures: a hierarchical place...
Giovanni Conforti, Damiano Macedonio, Vladimiro Sa...
SENSYS
2004
ACM
15 years 3 months ago
A sensor network application construction kit (SNACK)
We propose a new configuration language, component and service library, and compiler that make it easier to develop efficient sensor network applications. Our goal is the constr...
Ben Greenstein, Eddie Kohler, Deborah Estrin
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 3 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...