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CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
15 years 1 months ago
Induction-Oriented Formal Verification in Symmetric Interconnection Networks
The framework of this paper is the formal specification and proof of applications distributed on symmetric interconnection networks, e.g. the torus or the hypercube. The algorithms...
Eric Gascard, Laurence Pierre
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
15 years 4 months ago
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimso...
ITCC
2005
IEEE
15 years 3 months ago
A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs
The interconnection network plays an important role in the performance and energy consumption of a Networkon-Chip (NoC) system. In this paper, we propose a RDT(2,2,1)/α-based int...
Yang Yu, Mei Yang, Yulu Yang, Yingtao Jiang
JSSPP
2004
Springer
15 years 3 months ago
Multi-toroidal Interconnects: Using Additional Communication Links to Improve Utilization of Parallel Computers
Three-dimensional torus is a common topology of network interconnects of multicomputers due to its simplicity and high scalability. A parallel job submitted to a three-dimensional...
Yariv Aridor, Tamar Domany, Oleg Goldshmidt, Edi S...
NPC
2004
Springer
15 years 3 months ago
A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes
Massively parallel computing systems are being built with thousands of nodes. Because of the high number of components, it is critical to keep these systems running even in the pre...
Nils Agne Nordbotten, María Engracia G&oacu...