Sciweavers

689 search results - page 109 / 138
» Proposal of High Level Architecture Extension
Sort
View
RV
2009
Springer
155views Hardware» more  RV 2009»
15 years 2 months ago
Hardware Supported Flexible Monitoring: Early Results
Monitoring of software’s execution is crucial in numerous software development tasks. Current monitoring efforts generally require extensive instrumentation of the software or d...
Antonia Zhai, Guojin He, Mats Per Erik Heimdahl
HPCA
2009
IEEE
15 years 10 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
WORDS
2002
IEEE
15 years 2 months ago
Service Differentiation of Communication-bound Processes in a Real-Time Operating System
The majority of today’s Internet-based services are generally not concerned about the level of Quality of Service (QoS) presented to their users. For many such services, however...
Domenico Cotroneo, Massimo Ficco, Mauro Gargiulo, ...
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
15 years 4 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
DAC
2002
ACM
15 years 10 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy