689 search results - page 125 / 138 » Proposal of High Level Architecture Extension |
DAC
2002
ACM
15 years 10 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
IROS
2009
IEEE
15 years 4 months ago
2009
IEEE
— In multi-robot systems, task allocation and coordination are two fundamental problems that share high synergy. Although multi-robot architectures typically separate them into d...
86
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IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
107
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PPOPP
2003
ACM
15 years 2 months ago
2003
ACM
Large-scale cluster-based Internet services often host partitioned datasets to provide incremental scalability. The aggregation of results produced from multiple partitions is a f...